Chapter 3: The Future of 8 Chip Technologies

The life-cycle of 8 chip technologies: From first realization to first killer product, it takes 15 to 35 years.
The life-cycle of 8 chip technologies: From first realization to first killer product, it takes 15 to 35 years.

We select eight silicon chip technologies, which play significant roles in the decade 2010–2020 and beyond for the development of high-performance, low-energy chips. In the spirit of the 25-years rule, all of these technologies have been demonstrated, and some, in fact, are very mature and yet are worth to be revisited at the nano-scale.
The bipolar transistor remains superior in transconductance and bandwidth, and the complementary cross-coupled nano-pair can become the best ultra-low-energy signal-regenerator.
MOS and CMOS circuits continue to be the most effective solutions for giant- scale integration in a silicon-on-insulator technology. However, the end of progress with just scaling down transistor dimensions is near, and this is not a matter of technology capability, but one of atomic variance in 10 nm transistors. Once only ~6 doping atoms are responsible for their threshold and voltage gain, 95% of these transistors would have between 1 and 9 such atoms. Their threshold would vary more than their supply voltage. We show that, at these dimensions, not a transistor, but the cross-coupled pair of CMOS inverters is the elementary and necessary signal regenerator at the heart of ultra-low-voltage differential logic.
This assembly of four transistors is the perfect target for 3D integration at the transistor-level on-chip, and selective Si epitaxy is shown as an exemplary solution, including self-assembly eliminating certain lithography steps. This optimized 4T building block enables a 6T SRAM memory cell scalable to a 2020 density competitive with a DRAM cell, which cannot be scaled because of capacitor size and transistor leakage.
The 4T block is also the key accelerator in the differential logic HIPERLOGIC, exemplified by an n-bit by n-bit multiplier, which also illustrates the importance of new circuit architectures. DIGILOG, a most-significant-bit-first multiplier, has a complexity O(3n) versus O(n²/2) in commonly used Booth multipliers. With HIPERLOGIC, a 16 x 16 bit multiplier is projected to require only 1fJ per multiplication in 2020, about 1,000-times less than the status in 2010 and 10-times less than a synapse in the human brain. Therefore, processing has the potential to become 1,000-times more energy efficient within a decade.
The 3D integration of chips has become another key contributor to improve the overall energy efficiency of systems-of-chips incorporating sensing, transceiving, and computing.


Bernd Hoefflinger