CHIPS 2020

Interconnects on-chip between transistors and between functions like processors and memories, between chips on carriers or in stacks, and the communication with the outside world have become a highly complex performance, reliability, cost, and energy challenge.
Twelve layers of metal interconnects, produced by lithography, require, including the contact vias, 24 mask and process cycles on top of the process front-end. The resulting lines are associated with resistance, capacitance and inductance parasitics as well as with ageing due to high current densities.
Large savings in wiring lengths are achieved with 3D integration: transistor stacking, chip stacking and TSV’s, a direction, which has exploded since 2005 because of many other benefits and, at the same time, with sensitive reliability and cost issues. On top of this or as an alternative, non-contact interconnects are possible with capacitive or inductive coupling. Inductive in particular has proven to be attractive because its transmission range is large enough for communication in chip stacks and yet not too large to cause interference.
Optical transmitters based on integrated III-V compound-semiconductor lasers and THz power amplifiers compete with ascending low-cost, parallel-wire transmitters based on BiCMOS technologies. Parallel mm-wave and THz transceiver arrays enable mm-wave radar for traffic safety and THz computed- tomography.
In spite of all these technology advances, the power efficiency of data communication will only improve 100x in a decade. New compression and architectural techniques are in high demand.