CHIPS 2020

Barry Pangrle is a Solutions Architect for Low Power in the Engineered Solutions Group at Mentor Graphics Corporation. He has a B.S. in computer engineering and a Ph.D. in computer science, both from the University of Illinois at Urbana-Champaign. He has been a faculty member at University of California, Santa Barbara and Penn State University, where he taught courses in computer architecture and VLSI design while performing research in high-level design automation.
Barry has previously worked at Synopsys, initially on high-level design tools and then later as an R&D director for power optimization and analysis tools. He was the Director of Design Methodology for a fabless start-up company and has also worked at a couple of privately held EDA companies, where he focused on design automation tools for low power/energy designs. He has published over 25 reviewed works in high level design automation and low power design and served as a Technical Program Co-chair for the 2008 ACM/IEEE International Symposium on Low Power Electronics Design (ISLPED). He was also actively involved with the technical program committees for ISLPED and DAC for 2009 and was one of the General Co-Chairs for ISLPED 2010.